1. Field of the Invention
The present invention generally relates to a plating analyzing method and apparatus, and especially relates to such a method and apparatus in which a Laplace's equation is made discrete by the Finite Volume Method.
2. Description of the Related Art
As the design rule for fabricating semiconductors such as LSI is reduced more and more, large scale integration technology, chip downsizing technology, and SOC (System ON a Chip) technology for mixing logic and memory devices have been recently promoted to be developed. As these technologies advance, it has been strongly required to increase the number of bonding pads formed on one chip surface and miniaturize outer wirings connecting such bonding pads and inner wirings within the chip.
Multiple wiring structure having dual damascene wiring structure using Cu material has been adapted for semiconductors. The dual damascene wiring structure has good planarity of each wiring layer because each wiring is planarized by the CMP method. Therefore, electric short circuit between wiring layers can be easily inhibited, and that is especially preferable for the purpose of multiplying layers.
Cu material used for wiring layers and vertical wirings for via, etc. is deposited usually by an electroplating process. Because of the wiring rule progress, semiconductors having wiring distances less than several ten nm have been announced. On the other hand, larger wafers such as 300 mm diameter wafers for fabricating semiconductor chips are promoted. Under this situation, it is desired to form a Cu layer having uniform thickness over the whole surface of a wafer. As for semiconductors having high speed operation purpose, Au material is now considered to be used for wirings and substrate penetrating electrodes in order to reduce wiring resistances.
As a method for forming such bonding pads or wirings, an electroplating method, one of wet processes, can be employed. In the electroplating method, a conductor to be plated is placed as a cathode in a plating bath filled with plating liquid. Metal material for plating is also placed as an anode in the plating bath. And electric power is supplied between the anode and the cathode to form plating film or layer on the surface of the cathode conductor.
A plating analyzing method is proposed, in which a computer is used for numerically analyzing the condition of electroplating in order maximize a speed for forming electroplating on the cathode and optimize the arrangement of the anode. For example, Japanese Patent Laid-open Publications Nos. 2002-180295 and 2001-152397 propose a plating technique where in a plating system having an anode, a cathode and plating liquid, a Laplace's equation as a controlling equation is made discrete by the Finite Element Method (FEM) to obtain electric current densities and potential distribution in the system.
In the Finite Element Method, the system is finely divided into many meshes, and a node of each mesh is given unknown quantity such as potential, and a Laplace's equation is made discrete. Potentials between nodes are represented by interpolating functions. In order to obtain equations at nodes, simultaneous equations are calculated with using weighting functions.
FIG. 1 shows an electroplating apparatus 100, which comprises an anode 101, a cathode 102, and plating liquid 103. In this apparatus 100, plating film or layer is selectively deposited onto an exposed portion of conductor 102a of the cathode 102, which is in contact with the plating liquid 103. In this case, polarization voltage η generates on the conductor 102a surface of the cathode. As shown in FIG. 1, the electroplating system is made discrete by Finite Element Method, and boundaries between the conductor 102a and the insulator 102 become nodes a1 and a2. To each of the nodes a1, a2, two potentials Vc and Vc+η should be designated. In this case, an interpolation error due to the two potentials designated at the nodes a1, a2 affects neighborhood nodes b1-b6, resulting in a problem that an analysis error becomes larger.
Further, in the Finite Element Method applied to the nodes a1, a2 as shown in FIG. 1, plating electric currents are represented at both sides of the conductor 102a surface, and therefore electric current is not conserved between an element on the conductor 102a side of the conductor surface 102a-1 and an element on the plating liquid 103 side of the conductor surface 102a-1. Accordingly, another problem is that an electric current flowing through the boundary (conductor surface 102a-1) cannot be accurately calculated.
In order to solve these problems, it is possible to finely divide elements into small pieces to have many nodes on the conductor surface. However, as the number of elements increases, the time required for analyzing becomes longer.